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Efficient Distributed On-Chip Decoupling Capacitors for Nanoscale ICs

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4 Author(s)
Popovich, M. ; QCT, Qualcomm Corp., San Diego, CA ; Friedman, E.G. ; Secareanu, R.M. ; Hartin, O.L.

A distributed on-chip decoupling capacitor network is proposed in this paper. A system of distributed on-chip decoupling capacitors is shown to provide an efficient solution for providing the required on-chip decoupling capacitance under existing technology constraints. In a system of distributed on-chip decoupling capacitors, each capacitor is sized based on the parasitic impedance of the power distribution grid. Various tradeoffs in a system of distributed on-chip decoupling capacitors are also discussed. Related simulation results for typical values of on-chip parasitic resistance are also presented. The worst case error is 0.003% as compared to SPICE.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:16 ,  Issue: 12 )

Date of Publication:

Dec. 2008

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