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Thermal Via Allocation for 3-D ICs Considering Temporally and Spatially Variant Thermal Power

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4 Author(s)
Hao Yu ; Berkeley Design Autom., Santa Clara, CA ; Yiyu Shi ; Lei He ; Tanay Karnik

The existing 3-D thermal-via allocation methods are based on the steady-state thermal analysis and may lead to excessive number of thermal vias. This paper develops an accurate and efficient thermal-via allocation considering the temporally and spatially variant thermal-power. The transient temperature is calculated by macromodel with a one-time structured and parameterized model reduction, which also generates temperature sensitivity with respect to thermal-via density. The proposed thermal-via allocation minimizes the time-integral of temperature violation, and is solved by a sequential quadratic programming algorithm with use of sensitivities from the macromodel. Compared to the existing method using the steady-state thermal analysis, our method in experiments is 126 times faster to obtain temperature, and reduces the number of thermal vias by 2.04 times under the same temperature bound.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:16 ,  Issue: 12 )