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A new floating-point fused multiply-add (FMA) design for the execution of (A times B) + C as a single instruction is presented. The bridge fused multiply-add unit is a design intended to add FMA functionality to existing floating-point coprocessor units by including specialized hardware that reuses floating-point adder and floating-point multiplier components. The bridge unit adds this functionality without requiring an overhaul of coprocessor control units and without degrading the performance or parallel execution of addition and multiplication single instructions. To evaluate the performance, area, and power costs of adding a bridge FMA unit to common floating-point execution blocks, several circuits including a double-precision floating-point adder, floating-point multiplier, classic FMA, and a bridge FMA unit have been designed and implemented with AMD 65-nm silicon-on-insulator technology to provide a realistic and fair analysis of the presented FMA hardware tradeoffs.