Skip to Main Content
Extrinsic source/drain series resistance (R SD) is becoming inevitably dominant in state-of-the-art CMOS technologies as the intrinsic device resistance continues to scale with channel length dictated by the Moore's Law. As a result, advanced scaling techniques to achieve a lower intrinsic device resistance become less effective, particularly for NMOSFETs. With an attempt to better understand R SD impacts and identify the next key technology enabler, high-performance strained NMOSFETs featuring metallized (NiSi) source/drain extension (M-SDE) are investigated due to its cost-effective process and good short-channel scalability. The spacing between metallized extension and gate electrode edge is shown to play a very important role in R SD reduction and can significantly affect the electrical characteristics of M-SDE NMOSFETs. Tradeoff between R SD reduction and device integrity like junction leakage and reliability is found when the extension-to-gate edge spacing is modulated. On the other hand, by optimizing the NiSi-to-gate edge spacing, M-SDE NMOSFETs exhibit a higher on-current (I ON) and a higher strain sensitivity while maintaining comparable drain-induced barrier lowering, subthreshold swing, I OFF , and hot-carrier reliability as compared with the conventional SDE devices.