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Devices based on nanotubes and nanowires have been a popular research topic in the recent years. Many groups have shown promising experimental results in this area. In this paper, we examine the expected performances of 1-D and 2-D MOSFETs by numerical simulation and analytical models. We show that 1-D devices are not necessarily better than 2-D devices for future technologies, especially for low-channel densities and narrow gate widths, due to the parasitic capacitances and screening of the adjacent channels. For example, the delay improvement is overestimated from the intrinsic cases by at least 30%-60% from ignoring parasitics and channel screening effects, for Wgate<10 Lg and channel densities from 400 to 25 mum. We propose a methodology for 1-D device design optimization, and a possible scaling path of 1-D devices down to 11 nm node. The analytical model is a first step toward a compact model for 1-D FETs.