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Cable discharge events (CDEs) have been found to be the major root cause of inducing hardware damage on Ethernet ICs of communication interfaces in real applications. Still, there is no device-level evaluation method to investigate the robustness of complementary metal-oxide-semiconductor (CMOS) devices against a CDE for a layout optimization in silicon chips. The transmission-line pulsing (TLP) system was the most important method used to observe the electrical characteristics of semiconductor devices under human-body model (HBM) electrostatic discharge (ESD) stress. To understand the physical characteristics and CDE robustness of on-chip protection devices, the long-pulse transmission-line pulsing (LP-TLP) system is proposed in this paper and used to simulate the influence of CDE on Ethernet-integrated circuits. The secondary breakdown characteristics of the CDE protection devices under different layout styles and parameters can be measured and analyzed by the proposed LP-TLP with pulsewidths of 500 or 1000 ns. Furthermore, measured results using the LP-TLP system are compared with results measured by the traditional 100-ns TLP system. The experimental results with silicon devices in 0.18-mu m CMOS process have shown that the CDE robustness of n-channel metal-oxide-semiconductor (NMOS) and p-channel metal-oxide-semiconductor (PMOS) devices in deep-submicrometer CMOS technology is much lower than their HBM ESD robustness. By using the proposed LP-TLP system, one set of design rules for I/O devices to sustain high CDE robustness in a given CMOS process can be evaluated and built up for chip layout.