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Reduced pull-in time of phase-locked loops using a simple nonlinear phase detector

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1 Author(s)
P. Larsson ; Dept. of Phys. & Meas. Technol., Linkoping Univ., Sweden

For a single-loop frequency synthesiser, there is a trade-off between time-to-lock and output phase-noise. To lock a PLL quickly, a high natural frequency (ωn) is required, while a low ωn is necessary to obtain good jitter damping. The author presents a technique to reduce the time to lock of a frequency synthesiser PLL without changing the jitter transfer function

Published in:

IEE Proceedings - Communications  (Volume:142 ,  Issue: 4 )