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Systematic design space exploration for customisable multi-processor architectures

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3 Author(s)
Cope, B. ; Dept. of Electr. & Electron. Eng., Imperial Coll. London, London ; Cheung, P.Y.K. ; Luk, W.

A systematic approach to design space exploration of customisable options for multi-processor architectures is presented. This approach is used to explore a parameterisable system model as a part of a novel exploration tool. Architecture trends are analysed through the variation of prefabrication choice of number of processing elements (PEs) and cache size. Of note, is the relationship between multi-threading and off-chip memory access. This is shown to reduce performance by up to five times for a decimation case study. From the analysis of architecture trends, a post-fabrication choice of processing pattern is shown to provide up to three times improvement for a negligible area cost. In verification, the system model mimics the performance of sample graphics processors. This is achieved with a run time of only five minutes for a decimation case study with a model setup of eight processing elements and 16 KB cache.

Published in:

Embedded Computer Systems: Architectures, Modeling, and Simulation, 2008. SAMOS 2008. International Conference on

Date of Conference:

21-24 July 2008