Cart (Loading....) | Create Account
Close category search window
 

Analysis of Clock-Jitter Effects in Continuous-Time \Delta \Sigma Modulators Using Discrete-Time Models

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Chopp, P.M. ; Dept. of Electr. & Comput., McGill Univ., Montreal, QC ; Hamoui, A.A.

This paper proposes a simple discrete-time (DT) modeling technique for the rapid, yet accurate, simulation of the effect of clock jitter on the performance of continuous-time (CT) DeltaSigma modulators. The proposed DT modeling technique is derived from the impulse-invariant transform and is applicable to arbitrary-order lowpass and bandpass CT DeltaSigma modulators, with single-bit or multibit feedback digital-to-analog converters (DACs) employing delayed return-to-zero (RZ) or non-return-to-zero (NRZ) rectangular pulses. Its accuracy is independent of both the power spectrum of the clock jitter and the loop transfer function of the DeltaSigma modulator. The proposed DT modeling technique is validated (for both independent and accumulated clock-jitter errors) against accurate simulations in SIMULINK, using behavioral blocks developed to directly simulate RZ or NRZ DACs with clock jitter. It is subsequently applied to various CT DeltaSigma modulator architectures (low- pass and bandpass, with single-bit and multibit DACs) to study the relative effectiveness of different feedback-DAC pulsing schemes (NRZ, RZ, RZ with fixed on-time, and RZ with fixed off-time) in minimizing the modulator sensitivity to clock jitter. The performance of each architecture is compared as a function of clock jitter, thereby offering a valuable reference for selecting a rectangular feedback-DAC pulse shape when designing CT DeltaSigma analog-to-digital converters.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:56 ,  Issue: 6 )

Date of Publication:

June 2009

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.