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FPGA-Based Digital Pulsewidth Modulator With Time Resolution Under 2 ns

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4 Author(s)
Huerta, S.C. ; Univ. Politec. de Madrid, Madrid ; de Castro, A. ; Garcia, O. ; Cobos, J.A.

This paper proposes a new digital pulsewidth modulation (DPWM) architecture that takes advantage of the field-programmable gate array's (FPGA) advanced characteristics, especially the delay-locked loop (DLLs) present in almost every FPGA. The proposed DPWM combines a synchronous (counter-based) block with an asynchronous block for increased resolution without unnecessarily increasing the clock frequency. The experimental results show an implementation in a low-cost FPGA (Xilinx Spartan-3) that uses an external 32 MHz clock for a final time resolution under 2 ns.

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Power Electronics, IEEE Transactions on  (Volume:23 ,  Issue: 6 )