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A 10b 1 GS/s ADC employing a single channel cascaded folding architecture is presented. Conversion speed of 1 GS/s is attained by incorporating low-power distributed track-and-hold amplifiers after each folder. This ADC achieves a record 55.6 dB peak SNDR and a 64 dB peak SFDR and sustains a latency of one clock cycle. DNL and INL at 1 GS/s sampling rate are measured 0.4 LSB and 1.1 LSB. Fabricated in a 0.35 mum BiCMOS process, the ADC consumes 2 W from a 3.5 V supply.
Date of Conference: 13-15 Oct. 2008