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Power rail logic: a low power logic style for digital GaAs circuits

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4 Author(s)
Chandna, A. ; Joint Motorola/Cascade Libr. Dev. Center., Tempe, AZ, USA ; Brown, R.B. ; Putti, D. ; Kibler, C.D.

This paper describes a new logic style called Power Rail Logic (PRL), which is compatible with direct-coupled FET logic (DCFL) circuits. Multiplexors, latches, flip-flops, and exclusive-OR gates can be built using this logic style. Compared to DCFL, PRL uses fewer transistors, has larger noise margins, and up to 40% lower power-delay products. A test chip containing 32-b barrel shifters designed in DCFL and in PRL was successfully fabricated and tested. Test results are given for both circuits

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:30 ,  Issue: 10 )