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We present a neural stimulator chip with an output stage (electrode driving circuit) that is fail-safe under single-fault conditions without the need for off-chip blocking-capacitors. To miniaturize the stimulator output stage two novel techniques are introduced. The first technique is a new current generator circuit reducing to a single step the translation of the digital input bits into the stimulus current, thus minimizing silicon area and power consumption compared to previous works. The current generator uses voltage-controlled resistors implemented by MOS transistors in the deep triode region. The second technique is a new stimulator output stage circuit with blocking-capacitor safety protection using a high-frequency current-switching (HFCS) technique. Unlike conventional stimulator output stage circuits for implantable functional electrical stimulation (FES) systems which require blocking-capacitors in the microfarad range, our proposed approach allows capacitance reduction to the picofarad range, thus the blocking-capacitors can be integrated on-chip. The prototype four-channel neural stimulator chip was fabricated in XFAB's 1-mum silicon-on-insulator CMOS technology and can operate from a power supply between 5-18 V. The stimulus current is generated by active charging and passive discharging. We obtained recordings of action potentials and a strength-duration curve from the sciatic nerve of a frog with the stimulator chip which demonstrate the HFCS technique. The average power consumption for a typical 1-mA 20-Hz single-channel stimulation using a book electrode, is 200 muW from a 6 V power supply. The silicon area occupation is 0.38 mm2 per channel.