Cart (Loading....) | Create Account
Close category search window
 

Seeing double

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)

This paper discusses double patterning lithography for chips' manufacture. This technique was first demonstrated by Belgium's Interuniversity Microelectronics Centre (IMEC) for the 32-nm node, using a combination of double-patterning and immersion lithography. Conceptually, it's simple: instead of exposing the photoresist layer once under one photomask, as in conventional optical lithography, this technique exposes it twice.

Published in:

Spectrum, IEEE  (Volume:45 ,  Issue: 11 )

Date of Publication:

November 2008

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.