Cart (Loading....) | Create Account
Close category search window

Low-Power SOC Design Using Configurable Processors-The Non-Nuclear Option

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Rowen, C. ; Tensilica Inc., Santa Clara ; Dixit, A. ; Leibson, S.

Power and energy dissipation are increasingly important in SOC design. Low operating power reduces end-product costs by reducing the size of power supplies and heat sinks and by eliminating active cooling. Low SOC energy dissipation reduces battery size and increases battery life in portable equipment. As the use of multiple processors grows in SOC design, to gain the programmability and flexibility benefits that processors provide, the need to reduce each processor's power and energy requirements also grows. Configurable processors can deliver dramatic gains in energy efficiency, relative to fixed-instruction-set processors. This energy advantage comes from three improvements. First, instruction-set extension tailors a configurable processor to target applications, which reduces the required number of execution cycles, drops the processor's required operating frequency, and consequently cuts operating power. Second, processor configuration removes unneeded features and further reduces the processor's operating power. Third, automated processor-generation tools permit logic optimization, signal switching reductions, and use of low-voltage circuits and fabrication processes. Real processor-core designs can achieve power dissipation approaching 20 muW/MHz at 0.8V and nearly 10 muW/MHz at 0.6V, using production 0.13 mum libraries.

Published in:

System-on-Chip, 2005. Proceedings. 2005 International Symposium on

Date of Conference:

17-17 Nov. 2005

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.