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Constant complexity scheduling for hardware multitasking in two dimensional reconfigurable field-programmable gate arrays

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4 Author(s)
S. Roman ; Departamento de Arquitectura de Computadores y Automatica, Universidad Complutense de Madrid, Spain ; H. Mecha ; D. Mozos ; J. Septien

Technological improvements achieved for reconfigurable hardware together with applications' increasing demand of flexibility and speed for complex applications, make run-time reconfigurable devices an interesting piece in the design of computing systems. Operating systems (OS) have to be extended with functionalities, which allow them to efficiently manage the field-programmable gate arrays (FPGA). A constant-complexity algorithm is presented that would be a part of such an extended OS. The algorithm decides the scheduling and placing of arrival tasks with real-time constraints in the FPGA device. It divides the FPGA area into four partitions of different sizes. Each partition has an associated queue where the hardware manager places each arriving task depending on its size, shape and real time parameters as deadline requirements. The algorithm may change the queue selection policy, partition strategies and the sizes or the number of partitions at run-time in order to adapt itself in function of special characteristics of task profiles, taking into account task sizes and execution times for tasks in each queue. The authors will present experimental results, which prove that our algorithm is as competitive as other complex 'area-greedy' algorithms for real applications with real-time deadline constraints.

Published in:

IET Computers & Digital Techniques  (Volume:2 ,  Issue: 6 )