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Bit-serial systolic architecture for 2-D non-separable discrete wavelet transform

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2 Author(s)
Mohanty, Basant Kumar ; Jaypee Inst. of Eng. & Technol., Guna ; Meher, P.K.

In this paper, we present a novel fully-pipelined bit-serial architecture for systolic implementation of non-separable two-dimensional discrete wavelet transform (2-D DWT). The computations which become redundant due to the decimation process are eliminated to obtain an efficient computing algorithm for the 2-D DWT. Moreover, the critical path is reduced in the proposed design to have a small bit-level clocking period of only one full-adder delay. Due to smaller cycle period and efficient computing scheme the proposed structure leads to less area-time complexity compared with the existing bit-serial structure. It is shown that the proposed structure requires less than 0.01% of the hardware of the existing bit-serial architecture for 2-D DWT; and involves nearly 2.63% of area-time complexity of the later in average for image of size (512 times 512) for word-length varying from 8 to 20, and for filter order K = 4, 6 and 8.

Published in:

Intelligent and Advanced Systems, 2007. ICIAS 2007. International Conference on

Date of Conference:

25-28 Nov. 2007