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This paper proposes a novel technique of contexts (configure information) switch scheme in the loop pipeline, which effectively reduces the reconfigure time and speedup the application. The target architecture is an embedded coarse-grained reconfigurable processor, which consists of a general processor and a coarse-grained reconfigurable cell array (RCA). The technique focuses on the kernel loop body which is bigger than RCA and makes sure each line of context is switched in order without interrupting the regular execution. The proposed technique has been verified in REMUS (reconfigurable multi-media system) with the integer discrete cosine transform (DCT) and the motion estimation (ME) of H.264 baseline. 3.5 times of performance increase has been achieved compared with the traditional reconfigurable processor PipeRench, MorphoSys and TI DSP TMS320DM642.