Selectively multiple-valued memory design using negative differential resistance circuits implemented by standard SiGe BiCMOS process

A novel multiple-valued memory circuit design using negative differential resistance (NDR) circuit based on standard 0.35 mum SiGe process is demonstrated. The NDR circuit is made of metal-oxide-semiconductor field-effect-transistor (MOS) and heterojunction-bipolar-transistor (HBT) devices, but it can show the NDR characteristic in its current-voltage curve by suitably designing the MOS widths/lengths parameters. The memory circuit use three-peak MOS-HBT-NDR circuit as the driver and three constant current sources as the load. During suitably controlling the current sources on and off, we can obtain a sequence of multiple-valued logic output.