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A 13-bit CMOS pipeline analog-to-digital converter (ADC) with improved sampling circuits is proposed. In the first pipeline stage, the high frequency performance of the sampling circuit is improved by reducing the on-resistances of the switches and the time skew between the sampling capacitors and the comparators. In the subsequent stages, the conventional sampling circuit is modified for low power design by reducing the loading of the residue amplifier. The prototype ADC has been fabricated in a 0.18-mum CMOS process. With a 2.4-MHz input and 2.5-MHz sampling rate, the measured peak SNDR and SFDR are 75.26 dB and 90.46 dBc respectively. And when the input frequency increases to 15.4 MHz, this converter still achieves a 70.36 dB SNDR and a 93.9 dBc SFDR. Furthermore, it is verified by code density test that the first stage with the improved sampling circuit still functions correctly with the input frequency up to 282 MHz. The power consumption including output pad drivers is 21 mW at 2.7-V power supply.