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A power-efficient 0.8 V, 9-bit, 20-MS/s pipelined ADC with opamp-shared loading-free architecture

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3 Author(s)
Hsin-Hung Ou ; Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan ; Soon-Jyh Chang ; Bin-Da Liu

This paper demonstrates a 0.8-V, 9-bit, 20-MS/s pipelined ADC with only 0.58 pJ-Volts/step. A novel circuit architecture which merges opamp-sharing with loading-free structure is proposed. Such mechanism effectively reduces the number of opamps as well as the capacitive loading. In addition, an inverse-flip-around sample-and-hold with unity-feedback factor is employed which further reduces the power consumption. Simulation results using a 0.18 mum CMOS 1P6M process demonstrate the power consumption of this pipelined ADC is 4.5 mW which amounts to a figure-of-merit of 0.58 pJ-Volts/step.

Published in:

Communications, Circuits and Systems, 2008. ICCCAS 2008. International Conference on

Date of Conference:

25-27 May 2008