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Analysis of Read Current and Write Trip Voltage Variability From a 1-MB SRAM Test Structure

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7 Author(s)
Fischer, T. ; Inst. of Tech. Electron., Tech. Univ. Munchen, Munich ; Amirante, E. ; Huber, P. ; Nirschl, T.
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We present an area efficient test structure that allows measurement of the statistical distribution of SRAM cell read currents and write trip voltages for 1 million SRAM core cells. The data taken from measurements of wafers fabricated with a 90-nm and 65-nm CMOS process flow show that the device variations are Gaussian distributed for more than 1 million devices, covering more than 5 sigma of variation. The analysis of the measured SRAM performances validate Monte Carlo simulations.

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Semiconductor Manufacturing, IEEE Transactions on  (Volume:21 ,  Issue: 4 )