Analysis of Read Current and Write Trip Voltage Variability From a 1-MB SRAM Test Structure

We present an area efficient test structure that allows measurement of the statistical distribution of SRAM cell read currents and write trip voltages for 1 million SRAM core cells. The data taken from measurements of wafers fabricated with a 90-nm and 65-nm CMOS process flow show that the device variations are Gaussian distributed for more than 1 million devices, covering more than 5 sigma of variation. The analysis of the measured SRAM performances validate Monte Carlo simulations.