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Aggressive technology scaling raises the need for efficient methods to characterize and model circuit variation at both the front and back end of line, where critical parameters such as threshold voltage and parasitic capacitance must be carefully modeled for accurate circuit performance. In this paper we address this need by contributing a test circuit methodology for the extraction of spatial, layout and size dependent variations at both device and interconnect levels. The test chip uses a scan chain approach combined with low-leakage and low-variation switches, and Kelvin sensing connections, providing access to detailed analog device characteristics in large arrays of test devices. Variation measurement using the designed test chip has proven successful for both device and interconnect test structures. The parameter extraction and variation analyses made possible by the variation test chip enable the identification of likely variation sources, quantification of circuit impact and sensitivity, and specification of layout practices for variation minimization.