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This paper describes a new design approach for a power amplifier (PA) of the highly efficient hybrid envelope elimination and restoration (H-EER) transmitter. Since the PA operates mostly at the average power region of the modulation signal, power-added efficiency (PAE) of the PA at the average drain voltage is very important for the overall transmitter PAE. Accordingly, the PA is designed to have a maximum PAE in that region. The performances of the proposed PA and a conventional PA under H-EER operation are evaluated via ADS and MatLab simulations using a behavioral large-signal model of a silicon LDMOSFET, which verifies that the proposed PA has significant advantages for the H-EER transmitter in both PAE and output power. A saturated amplifier, inverse class F, has been implemented using a 5-W peak envelope power LDMOSFET for 3GPP forward-link single-carrier wideband code-division multiple-access at 1 GHz with a peak-to-average power ratio of 9.8 dB. An envelope amplifier is built that has an efficiency of above 68% and peak output voltage of 31 V for an interlock experiment. The overall PAE of the transmitter with a conventional PA is 35.5% at an output power of 29.2 dBm. On the other hand, the transmitter with the proposed PA delivers significantly improved performances: PAE increased by 4% and output power by 2.5 dB. The H-EER transmitter has been linearized by the digital feedback predistortion technique. The measured error vector magnitude is reduced to 1.47% from 6.4%. These results clearly show that the proposed architecture is a good candidate for efficient linear transmitters.