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This letter reports on the implementation of high carbon content and high phosphorous content Si1-xCx layers in the source and drain regions of n-type MOSFET in a 65-nm-node integration scheme. The layers were grown using a novel epitaxial process. It is shown that by implementing stressors with x ap 0.01, nMOSFET device performance is enhanced by up to 10%, driving 880 muA/mum at 1-V V DD. It is also demonstrated that the successful implementation of Si1-xCx relies on the careful choice of integration and epitaxial layer parameters. There is a clear impact of the postepitaxial implantation and thermal treatment on the retained substitutional C content ([C sub]). Furthermore, adding a Si capping layer on top of the Si1 -xCx, greatly improves upon the stressors' stability during the downstream processing and the silicide sheet resistance.