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A VLSI architecture for the wavelet transform

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3 Author(s)
Brown, C.I. ; Sheffield Univ., UK ; Thacker, N.A. ; Yates, R.B.

This paper describes an architecture for efficient calculation of signed integer sparse matrix multiplication. The architecture allows high bit accuracy operations. The architecture has many possible applications. Its application to the wavelet transform and image coding is explored. The data path is described and it is shown that the wavelet transform can be performed using 14 bits to represent the coefficients and 22 bits to represent intermediate results. We conclude by mapping the wavelet algorithm onto the proposed architecture and summarising the advantages and disadvantages. It is also shown that synthesis of a high bit accuracy multiplication from a lower bit accuracy device is as efficient as using a high bit accuracy device

Published in:

Image Processing and its Applications, 1995., Fifth International Conference on

Date of Conference:

4-6 Jul 1995