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A Unifying Approach for Weighted and Diminished-1 Modulo 2^n+1 Addition

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2 Author(s)
Vergos, H.T. ; Dept. of Comput. Eng. & Inf., Univ. of Patras, Patras ; Efstathiou, C.

In this paper, it is shown that every architecture proposed for modulo 2n+1 addition of operands that follow the diminished-1 representation can also be used in the design of modulo 2n+1 adders for operands that follow the weighted representation. This is achieved by the addition of a constant-time operator composed of a simplified carry-save adder stage. The experimental results indicate that many architectures already proposed for the diminished-1 case, lead to very efficient adders for weighted operands, under this unifying approach.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:55 ,  Issue: 10 )

Date of Publication:

Oct. 2008

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