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Constrained Partial Response Receivers for High-Speed Links

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3 Author(s)
Ahmadi, M.R. ; Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Minneapolis, MN ; Jaekyun Moon ; Harjani, R.

This paper presents an architecture and an optimization framework that uses partial response (PR) equalization for high-speed links. PR equalization is achieved through a combined use of linear transmit equalization and decision feedback equalization (DFE). This technique outperforms full-channel/impulse equalization for a wide range of channels in wireline communication. The constrained PR response equalization technique presented here improves eye openings, reduces the overall bit error rate, and reduces crosstalk impact for a large class of channels while maintaining a simple implementation. The new transceiver architecture proposed is particularly well suited for high-speed multichannel applications due to the mitigated DFE loop timing constraint. In comparison with duobinary equalization, the proposed PR architecture improves the eye height and eye width of the receiver by 28% and 10%, respectively, at 10 Gb/s and by 19% and 7%, respectively, at 15 Gb/s. The performance improvements in comparison to impulse equalization are even larger.

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Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:55 ,  Issue: 10 )