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Device scaling of high performance MOSFET with metal gate high-k at 32nm technology node and beyond

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4 Author(s)
Xinlin Wang ; Res. Div., IBM Semicond. R&D Center, Hopewell Junction, NY ; Shahidi, G. ; Oldiges, P. ; Khare, M.

In this work, two different methodologies are used to quantitatively evaluate devices with metal high-k gate dielectrics for their scaling benefits over conventional polysilicon gate devices. For each method, device characteristics and ring oscillator delay calculations are performed. Our results show that aggressive channel length scaling continually provides transistor performance gain with the use of metal gate high-k technology. A band edge work function for the metal gate offers potential benefits for device scaling over conventional polysilicon gates for high performance (HP) application at the 32 nm CMOS technology node and beyond.

Published in:

Simulation of Semiconductor Processes and Devices, 2008. SISPAD 2008. International Conference on

Date of Conference:

9-11 Sept. 2008