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Threshold voltage-minimum gate length trade-off in buried channel PMOS devices for scaled supply voltage CMOS technologies

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5 Author(s)
Kizilyalli, I.C. ; AT&T Bell Labs., Orlando, FL, USA ; Rambaud, M.M. ; Duncan, A. ; Lytle, S.A.
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The trade-off between threshold voltage (VTh) and the minimum gate length (L/sub m/in) is discussed for optimizing the performance of buried channel PMOS transistors for low voltage/low power high-speed digital CMOS circuits. In a low supply voltage CMOS technology it is desirable to scale VTh and L/sub m/in for improved circuit performance. However, these two parameters cannot be scaled independently due to the channel punch-through effect. Statistical process/device modeling, split lot experiments, circuit simulations, and measurements are performed to optimize the PMOS transistor current drive and CMOS circuit speed. We show that trading PMOS transistor VTh for a smaller L/sub m/in results in faster circuits for low supply voltage (3.3 to 1.8 V) n/sup +/-polysilicon gate CMOS technology, Circuit simulation and measurements are performed in this study. Approximate empirical expressions are given for the optimum buried channel PMOS transistor VTh for minimizing CMOS circuit speed for cases involving: (1) constant capacitive load and (2) load capacitance proportional to MOS gate capacitance. The results of the numerical exercise are applied to the centering of device parameters of a 0.5 μm 3.3 V CMOS technology that (a) matches the speed of our 0.5 μm 5 V CMOS technology, and (b) achieves good performance down to 1.8 V power supply. For this process the optimum PMOS transistor VTh (absolute value) is approximately 0.85-0.90 V.

Published in:

Electron Device Letters, IEEE  (Volume:16 ,  Issue: 10 )