Junction charge-coupled devices for bit-level systolic arrays

The application of junction chargecoupled devices (JCCDs) within the concept of bitlevel systolic arrays is discussed. The extremely small basic memory cell and the low power dissipation of CCDs make it a candidate for bit-level systolic arrays if fast suitable logic functions can be realised. Junction charge-coupled logic (JCCL) provides a good solution to the large amount of local memory. The implicit regeneration of charge packets and the variety of logic functions are strong arguments for using junction CCDs. A JCCL inner-product step-processor is described.