By Topic

Bit-serial systolic sorting: general complexities and an implementation in VLSI

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Li, H.F. ; Concordia University, Department of Computer Science, Montreal, Canada ; Jayakumar, R. ; Sun, X.

Bit-serial systolic sorting in very large scale integration (VLSI) is considered. Lower bounds on the area, computation time, and flush time for such a sorter are derived for three different input formats, namely the bitwise, the wordwise and the unconstrained formats. The logic design and CMOS circuit design of an optimal bit-serial wordwise systolic sorter are presented. The performance characteristics of the designed chip are discussed.

Published in:

Computers and Digital Techniques, IEE Proceedings E  (Volume:134 ,  Issue: 3 )