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Hierarchical functional verification for cell-based design styles

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3 Author(s)
Chen, L.G. ; National Cheng Kung University, Department of Electrical Engineering, Tainan, Republic of China ; Lee, J.Y. ; Wang, J.F.

Special-purpose verification tools have been proposed recently to solve cell-based layout verification problems. The paper proposes a hierarchical netlist extractor, an electric rule checker and a connectivity checker. These verification tools are developed especially for the structured and hierarchical artwork data. A new solution for schematic-to-layout netlist comparison is also developed. The major advantages of these tools are the redundant modular design pattern can be completely neglected, and the functional connectivity can be checked completely. A number of practical chips have been checked as examples. Experimental results have shown that this hierarchical functional verification can be used efficiently for VLSI layout.

Published in:

Electronic Circuits and Systems, IEE Proceedings G  (Volume:134 ,  Issue: 2 )