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Partitioning concurrent VLSI simulation programs onto a multiprocessor by simulated annealing

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1 Author(s)
J. Sheild ; Loughborough University of Technology, Department of Electronic & Electrical Engineering, Loughborough, UK

Efficiently loading concurrent programs onto multiprocessor architectures is a graph partitioning problem where both the edges and vertices are weighted. The corresponding optimisation problem is computationally NP-hard, and the optimal solution can only be found by exhaustively examining all possible partitioning configurations. Near-optimal solutions can be found by using heuristic algorithms such as iterative improvement and simulated annealing. The simulated annealing heuristic is experimentally evaluated against simple iterative improvement for graphs representing the concurrent simulation programs of four VLSI circuits where the vertices were weighted. A simple cost function and an annealing schedule are presented for partitioning the graphs onto a star network of identical processors. Experimental results show that simulated annealing produces a better solution than simple iterative improvement but at the expense of considerable computer running times. It is suggested that the time required for simulated annealing to give better solutions than iterative improvement depends on the nature of distributions of weighted vertices and edges in the concurrent simulation graph as well as its size.

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IEE Proceedings E - Computers and Digital Techniques  (Volume:134 ,  Issue: 1 )