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Silicon-on-insulator technology

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1 Author(s)
Partridge, S.L. ; GEC Research Ltd., Hirst Research Centre, Wembley, UK

The last few years have seen considerable progress in the development of techniques for producing silicon-on-insulator (SOI) substrates suitable for fabrication of high performance devices/circuits. Among the most promising of the new ideas are those based on buried dielectric formation by ion implantation (oxygen or nitrogen), recrystallisation of deposited polycrystalline silicon-on-insulator (using lasers, electron beams, hot wires, strip heaters or incoherent light), and oxidation of porous silicon. A number of other techniques also show potential. The concept of SOI is not new, however. Attempts to grow single crystal semiconductor films on insulating substrates date back almost 40 years with the first successes in the growth of silicon layers in the early 1960s. During that period epitaxial silicon-on-sapphire (SOS) emerged as a viable approach to SOI, since when it has become a well established technology for MOS with a unique role to play in some important areas of application. The new substrate types promise to extend the range of applicability still further. Indeed, some workers predict a revolution, following which, for MOS technology at least, single crystal silicon substrates will play a minor role in comparison to SOI. This paper outlines these different approaches to SOI and reviews their advantages for a number of important application areas, placing particular emphasis on MOS technology. Applications such as VLSI, memory, structured, random and high speed logic, analogue circuit design and defence electronics are considered. Recent developments in the preparation of SOI substrates have led to the successful realisation of a range of novel `stacked┬┐┬┐ structures exploiting, for example, two (or more) independent layers of devices, common gates or common device channels. Progress in and the potential of this exciting new field of three-dimensional integration is reviewed also.

Published in:

Computers and Digital Techniques, IEE Proceedings E  (Volume:133 ,  Issue: 3 )