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The paper describes the dilemma of the merchant semiconductor company, where increased complexity of semiconductor devices results in increased development costs, while, in many cases, increased complexity means increased specialisation and therefore reduced volumes. The solution proposed is to transfer design to the equipment companies. This solution is only practical if the expertise of the chip designer is embodied in sophisticated computer aids. In this case, the merchant semiconductor company reduces to a silicon foundry. The paper goes on to discuss the two principal techniques available to achieve the above objective, namely gate arrays and the more recently introduced standard cell design methodology. Also discussed is the extension of the standard cell from relatively simple cells to larger parametric cells created to specification using silicon compilers. Some of the more detailed topics briefly discussed include stick diagrams as an alternative methodology, two-layer metal to aid autorouting, the importance of good logic simulation, trend curves for the next 10 years and prediction of some of the problems and some of the products which may result from increased scale of integration.