Referenced Items are not available for this document.
A bit level systolic array for computing the convolution operation is described. The circuit in question is highly regular and ideally suited to VLSI chip design. It is also optimised in the sense that all the cells contribute to the computation on each clock cycle. This makes the array almost four times more efficient than one which was previously described.
Published in:
Communications, Radar and Signal Processing, IEE Proceedings F
(Volume:131
,
Issue:
6
)
Date of Publication: October 1984
- Page(s):
- 632 - 637
- ISSN :
- 0143-7070
- Digital Object Identifier :
- 10.1049/ip-f-1:19840097
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 11 November 2008
- Issue Date :
- October 1984
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
