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The paper describes work being carried out at the Plessey Marine Research Unit on the application of VLSI building block and novel architecture to future generation sonar systems. The emphasis in on high speed good dynamic range and good accuracy in the arithmetic units and a design procedure which will enable the sonar signal processor to be designed by a system designer.
Communications, Radar and Signal Processing, IEE Proceedings F (Volume:131 , Issue: 3 )
Date of Publication: June 1984