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The paper is an exposition of some of the design principles involved in the development of a dynamically reconfigurable vector-slice processor. Implementable in terms of commercially available VLSI components, the reconfigurable processor is designed to meet the requirements of the numerical user who can avail himself of a tradeoff between parallel activity and numerical accuracy. To this end, the processing heart of the system can be dynamically altered by the user to enter one of a number of predefined configuration states, each one of which represents an altered level of parallelism balanced against the width of each parallel subprocessor in the configuration. The paper describes, in some detail, the structure of the processor in terms of both its control and data paths.