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A new compensation strategy reducing voltage/current distortion in PWM VSI systems operating with low output voltages

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2 Author(s)
Jong-Woo Choi ; Sch. of Electr. Eng., Seoul Nat. Univ., South Korea ; Seung-Ki Sul

In a voltage-fed PWM inverter, the relation between the reference voltage and the output voltage is nonlinear due to the dead time effect and the voltage drop of the switching devices. The nonlinear voltage distortion invokes serious problems such as current waveform distortion and deterioration of the performance. Especially, the clamping of current around the zero crossing point is the most serious problem in the low-frequency region. In this paper, the analysis of the zero current clamping phenomenon is discussed. From this analysis, a novel distorted voltage compensation method which eliminates zero current clamping is presented. Experimental results are also presented to demonstrate the validity of the proposed method

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IEEE Transactions on Industry Applications  (Volume:31 ,  Issue: 5 )