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This paper describes a microprogrammable arithmetic element (m.a.e.) which has been designed as an integrated circuit on a high-speed bipolar process using emitter coupled logic (e.c.l.). Although the m.a.e., which contains a multiplier and adder, is a general-purpose computing device, it is ideally suited to a variety of digital signal processing (d.s.p.) applications such as discrete Fourier transforms, correlators, digital filters, etc. After a brief introduction to d.s.p. systems, some applications of the m.a.e. are discussed in detail. The m.a.e. forms part of a d.s.p. chip set which also includes a pair of integrated circuits. These have been produced by using e.c.l. programmable logic arrays (p.l.a.s); they decode a conventional binary sequence into the various addressing sequences required by a radix-2 decimation-in-time f.f.t. algorithm. In the past, the sheer cost and complexity of d.s.p. systems has restricted the system designers to make use of minimum hardware configurations in order to produce a system of reasonable size. However, such design philosophy has to be reviewed in the light of l.s.i. technology which has provided cheaper and bigger memory systems, apart from other l.s.i. building blocks. This point has been stressed by considering the design of an f.f.t. system.