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CMOS mobility degradation coefficients at low temperatures

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2 Author(s)
Campbell, S.A. ; University of Minnesota, Department of Electrical Engineering, 139 Electrical Eng., Minneapolis, USA ; Andersen, P.

An AC measurement technique is applied to NMOS and PMOS devices fabricated using a 1.25 ¿m CMOS process. The parasitic resistance and mobility degradation coefficients have been extracted for temperatures between 25 K and 300 K. The NMOS parasitic resistance stays flat with temperature while the PMOS resistance rises sharply below 200 K, probably due to the light source/drain diffusion doping. The mobility reduction parameter ¿, shows a clear 1/T behaviour between 100 K and room temperature, with ¿ approaching unity for the PMOS devices. This may have serious implications for the performance of highly scaled devices which operate at high transverse electrical fields.

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Solid-State and Electron Devices, IEE Proceedings I  (Volume:135 ,  Issue: 1 )