By Topic

Efficient design rule checking using a scanline algorithm

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Thomas, P.R. ; University of Southampton, Department of Electronics and Computer Science, Southampton, UK ; Brown, A.D.

Design rule checking of integrated circuits requires many operations which manipulate and test geometric figures. Closer examination often reveals that some effort is duplicated by different operations on the same mask data. The paper describes a scanline based design rule checker which structures the mask data to allow common administrative operations to be separated from the main checking process. This structuring is made possible by a novel data structure, the `scanline history¿, and it is demonstrated experimentally that, after an initial preprocessing phase, the workspace and execution times required to perform design rule checking are 0(N0.5) and 0(N). The results indicate that rationalised scanline administration yields significant savings in overall execution time.

Published in:

Solid-State and Electron Devices, IEE Proceedings I  (Volume:134 ,  Issue: 2 )