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A new extraction technique for obtaining the parasitic source/drain resistance and the effective channel length of an MOS device at 77 K is presented. Unlike previous methods, both parameters are assumed to vary with the gate voltage. This results in positive and physically meaningful results at any temperature. Simulation results show that, in non-LDD devices, the source/drain resistance decreases and the effective channel length increases with gate bias, indicating that the gate dependence of both parameters is inherent to MOS devices.