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DRAM plate electrode bias optimization for reducing leakage current in UV-O3 and O2 annealed CVD deposited Ta2O5 dielectric films

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1 Author(s)
Madan, S.K. ; Semicond. Process & Design Center, Texas Instrum. Inc., Dallas, TX, USA

A new plate biasing scheme is described which allowed the use of 65% higher supply voltage without increasing the leakage current for the UV-O3 and O2 annealed chemical-vapor-deposited tantalum pentaoxide dielectric film capacitors in stacked DRAM cells. Dielectric leakage was reduced by biasing the capacitor plate electrode to a voltage lower than the conventionally used value of Vcc/2. Ta2O5 films with 3.9 nm effective gate oxide, 8.5 fF/μm2 capacitance and <0.3 μA/cm2 leakage at 100°C and 3.3 V supply are demonstrated.

Published in:

Electron Devices, IEEE Transactions on  (Volume:42 ,  Issue: 10 )

Date of Publication:

Oct 1995

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