By Topic

A fault-tolerant CEQRNS processing element for linear systolic array DSP applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Smith, J.C. ; Dept. of Adv. Design Technol., Motorola Inc., Austin, TX, USA ; Taylor, F.J.

The design of a Galois enhanced quadratic residue number system (GEQRNS) processor is presented, which can be used to construct linear systolic arrays. The processor architecture has been optimized to perform multiply-accumulate type operations on complex operands. The properties of finite fields have been exploited to perform this complex multiplication in a manner which results in greatly reduced hardware complexity. The processor is also shown to have a high degree of tolerance to manufacturing defects and faults which can occur during operation. The combination of these two factors makes this an ideal candidate for array signal processing applications, where high complex arithmetic data rates are required. A prototype processing element has been fabricated in 1.5 μm CMOS technology, which is shown to operate at 40 MHz

Published in:

Computers, IEEE Transactions on  (Volume:44 ,  Issue: 9 )