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Experimental 1 Mbit DRAM using power reduction techniques

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5 Author(s)
Kimura, Katsutaka ; Hitachi Ltd., Central Research Laboratory, Tokyo, Japan ; Kiyoo Itoh, B.S. ; Hori, Ryoichi ; Etoh, Jun
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One of the serious problems which must be overcome in realising a 1 Mbit DRAM is high-power dissipation associated with data-line charging and discharging. To solve this problem, this paper proposes the following three techniques, which permit power reduction by about one-quarter: a multidivided data-line structure, 512 refresh cycles and an on-chip voltage limiter circuit. These techniques are proven to be useful through the design and evaluation of an experimental n-MOS 1 Mbit DRAM with a 46 mm2 chip size. The chip fabricated provides a 295 mW operating power at a 260 ns cycle time despite the fast access time of 90 ns. The possibility of further power reduction is also described.

Published in:

Solid-State and Electron Devices, IEE Proceedings I  (Volume:132 ,  Issue: 1 )