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Hot-carrier effects in submicrometre MOS VLSI circuits are described in terms of (a) the hot-carrier injection mechanisms, (b) the device degradation, (c) the hot-carrier resistant device structures and (d) the hot-carrier phenomena under a bias of less than 3 V. Two significant hot-carrier injection mechanisms are proposed which are different from those of the channel hot-electron (CHE) and substrate hot-electron (SHE) injection as previously reported by Ning et al. They are (i) drain avalanche hot-carrier (DAHC) and (ii) secondarily generated hot-electron (SGHE) injection. Based on an experimental comparison of gate currents due to these mechanisms it is shown that DAHC imposes the most severe constraint on VLSI design. In addition, hot-carrier resistant device structures, such as an As-P double diffused drain (DDD) and lightly doped drain (LDD), are also described as so called `drain engineering techniquesÂ¿ to enhance reliability of MOS devices. Finally, in anticipation of a possible reduction in power supply voltages in the future, hot-carrier phenomena have been investigated at bias levels below 3 V, where hot carriers cannot obtain enough energy to surmount the Si-SiO2 barrier. The experimental results clearly show that device degradation due to hot-carrier injection occurs even at VD < 3 V. Thus, hot carrier effects remain one of the most stringent limiting factors affecting submicrometre MOSFETs, even after the power supply voltage is reduced.