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Low power design under parameter variations

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2 Author(s)
Swarup Bhunia ; Case Western Reserve University, USA ; Roy Kaushik

Design considerations for low-power operations and robustness with respect to variations typically impose contradictory design requirements. Low-power design techniques such as voltage scaling, dual-Vth and gate sizing can have large negative impact on parametric yield under process variations . In this tutorial, we focus on circuit/architectural design techniques for low power under parameter variations. We consider both logic and memory design and encompass modeling, analysis as well as design methodology to simultaneously achieve low power and variation tolerance. Design techniques to minimize power under parametric yield constraint as well as major process adaptation techniques using voltage scaling, adaptive body biasing or logic restructuring will be presented. Techniques to deal with within-die parameter variations in logic and memory circuits primarily caused by random dopant fluctuations will be discussed. Finally, we will discuss temperature-aware design, dynamic adaptation to temperature and on-going research activities on low-power and variation tolerant multi-core processor design.

Published in:

2008 IEEE International SOC Conference

Date of Conference:

17-20 Sept. 2008